Spin torque random access memory (ST-MRAM) design spaces down to CMOS 22 nm technology node are explored using a dynamic magnetic tunneling junction (MTJ)-CMOS model. The coupled dynamics of MTJ and CMOS is modeled by a combination of MTJ micromagnetic simulation and CMOS SPICE circuit simulation. The paper analyzes trade-offs between MTJ current threshold, MTJ thermal stability and CMOS driving strength. The analysis provides information on physics requirements and technology bottlenecks for MTJ to achieve maximum capacity supported by CMOS 22 nm technology node. Magnetic solutions for MTJ to fully achieve CMOS 22 nm potential capacities are reviewed.