This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits, with a special emphasis on the current challenges concerning the physical modeling of ultra-scaled devices (in the deca-nanometer range) and new device architectures (Silicon-on-insulator, multiple-gate, nanowire MOSFETs). After introducing the classification and the terminology used in this paper, we firstly present the basis of the different transport models used in device-level simulation (drift-diffusion, hydrodynamic, Monte-Carlo and some approximated and exact quantum-mechanical based approaches). We also focus on the main emerging physical phenomena affecting ultra-short MOSFETs (quantum effects, tunneling current, ballistic operation) and the methods envisaged for taking them into account at device simulation level. Several examples of device simulation are given at the end of this first part, including recent results on fully-depleted SOI and multiple-gate devices. In the second part, we briefly survey the different circuit-level modeling approaches (circuit-level simulation, Mixed-Mode, 3-D simulation of portions of circuits) of single-event effects in integrated circuits. The SEU in advanced SRAM and SEE mechanisms in logic circuits are reminded. The production and propagation of digital single-event transients (DSETs) in sequential and combinational logic, as well as the soft error rate trends with scaling are particularly addressed. Recent bibliographical examples of simulation in SRAMs and logic circuits are presented and discussed to illustrate these topics at circuit-level.