An equivalent single conductor (ESC) model is proposed for the time domain analysis of a CMOS gate driving a high speed interconnect consisting of a single wall carbon nanotube (SWCNT) bundle. The computed responses to a step-input voltage are compared to the ones of a multiconductor transmission line (MTL) model. The results obtained are in very good agreement. The 50% time delay tpd of the nano-interconnect is predicted by means the MTL and ESC model and by applying an analytical formulation. The sensitivity analysis of tpd is carried out with respect to the number of the conductive tubes in the bundle, the length and the terminal equivalent capacitance of the interconnect configuration.