A direct digital synthesizer (DDS) implemented in InP double heterojunction bipolar transistor technology is reported. The DDS has a 12 b phase accumulator and a ROM-based phase converter. The DDS is capable of synthesizing output frequencies up to 12 GHz in steps that are 1/4096 of the 24 GHz clock rate. The worst case measured spurious free dynamic range (SFDR) is 30.7 dBc and the average SFDR over all frequency control words is 40.4 dBc. The DDS test circuit is implemented with 4470 transistors and it consumes 19.8 W of power.