Buried channel CTD's must be designed to isolate their depleted channels from charge generated in the substrate by penetrating radiation to obtain optimum transient radiation hardness or radiation detector time response. This can be achieved by employing an NPN structure so that the electrons generated in the N substrate are confined by the reverse biased P-N junction from diffusing across the P layer to the N channel. Unfortunately, moderate doped P layers often do not have the necessary conductivity required experimentally to pin the junction bias during intense transient radiation. However, the use of P+ layers is shown to accomplish this purpose. Although buried channel CTD's are used as experimental examples, the principles are applicable to a wide range of MOS charge storage devices. One potential application is in the reduction of alpha particle induced soft errors associated with conventional packaging. This soft error problem is a significant issue in future small cell VLSI development.