As the digital signal processing hardware system grow in complexity and power consumption, the trend is system design has been to design at higher levels of abstraction. A new design methodology supports the idea of designing at a higher level of specification which implies the functional and quantitative behaviours of the required signal processor and then transforming this into a hardware description language. Such kind of design methodology can reduce the overall design time and estimate the performance of hardware implemented system. In this article, a prototype architecture of fixed-point digital signal processor is modelled using RT-SPA and then be translated into VHDL-AMS, and synthesized using 0.18 mum CMOS standard cell library with a SYNOPSYStrade tool. It enables low bit error rate, low power consumption and small area, as well as can be readily sent for fabrication in a CMOS process.