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Evaluation of a Packet Switching Algorithm for Network on Chip Topologies using a Xilinx Virtex-II FPGA based Rapid Prototyping System

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4 Author(s)
Becker, J.E. ; Inst. for Inf. Process. Technol., Karlsruhe Univ. ; Bieser, C. ; Becker, J. ; Mueller-Glase, K.-D.