A large amount of work is in progress on reliability block diagramming (RBD) techniques. Another body of dynamic research is in digital testing of embedded systems with very large scale integration (VLSI) circuits. Each embedded system, whether simple or complex, can be decomposed to consist of components (blocks) and interconnections or transmissions (links) within an s-source (input) and t-target (output) setup. There are three tools proposed in this study. The first tool, using a novel "compression algorithm" is capable of reducing any complicated series-parallel system (not complex) to a visibly easy sequence of series and parallel blocks in a reliability block diagram by first finding all existing paths, then algorithmically compressing all redundant component duplications, and finally calculating an exact reliability and creating an encoding of the topology. A second tool is to decode and retrieve an already coded s - t dependency relationship using post-fix notation for series-parallel or complex systems. A third tool is an approximate fast upper-bound (FUB) s - t reliability computing algorithm designed for series-parallel systems, to perform state enumeration in a hybrid form assisted by the Polish encoding approach on non-series-parallel complex systems to compute the exact s (source)-t (target) reliability. Various examples illustrate how these tools work satisfactorily in unison. Further research with the OVERLAP method is in progress to reduce the computation speed by a thousand fold for a grid of 19 nodes without sacrificing any accuracy.