We have developed a new device structure suitable for high-performance and high-power mixed signal large scale integrations (LSIs) using 0.35-μm SOI complementary bipolar transistors. The new structure is composed of array transistors for various operating currents and flexible U-groove (trench) layout for high-power transistors. Thermal simulation results showed that the thermal resistance could be reduced by 40% by using the flexible U-groove layout. Test structure measurements showed that the maximum operating currents of a double polysilicon self-aligned NPN transistor were improved by 2 and 3.5 times by using ballasting resistors and ballasting resistors with flexible U-groove layout, respectively. The effects of the transistor structure on the thermal resistance and the maximum operating current were discussed.