For efficient full-chip circuit simulation and device performance optimization in RF system-on-a-chip (SoC) design, we propose a novel methodology to generate a compact macro-model for on-chip passive components, considering parasitics. Our approach is based on the recently proposed vector potential equivalent circuit (VPEC) model for the passive sparsification of the inductance matrix, a hierarchical s-domain circuit reduction to generate a reduced driving-point impedance function, and Brune's one-port network synthesis to realize the impedance function by a low-order RLCM ladder circuit as the compact macro-model. We improved the VPEC model generation via a window-based extraction and achieve extraction speedup by 100 times. We also propose an efficient scaling scheme during hierarchical model reduction to improve numerical stability of the reduction process. Several industry examples are presented, including transmission lines and spiral inductors. The synthesized lower-order macro-model is accurate up to 10 GHz with 1000 times simulation speedup.