A new architecture for pixel-level parallel image processing in the pulse domain for CMOS vision chips has been developed. Image processing such as edge enhancement, edge detection, and blurring are realized based on suppression and promotion of digital pulses; the pixel value is represented by the frequency of digital pulses by use of a pulse-frequency modulation (PFM) photosensor or that with an in-pixel 1-bit analog-to-digital converter. The proposed architecture is suitable for low-voltage operation in deep-submicrometer technologies because the image processing is implemented by 1-bit fully digital circuits with a small number of logic gates. The principles of the image processing are addressed. We have fabricated a 16 × 16-pixel prototype vision chip. The relationship between illumination and the output pulse frequency is characterized. Step responses of the prototype vision chip for fundamental image processing operations show good agreement with those expected by correlation-based spatial filtering. A simple image binarization method specific to our architecture is also presented. The histograms of the intervals of the output pulses after image processing show multiple peaks, which indicates that averaging of the intervals is required for longer periods to achieve higher image-processing quality. To improve the linearity of pulse frequency dependence on illumination, usage of random clocks is discussed.