The impacts of various layout configuration and device dimensions on device performance are examined. The geometrical scaling issues including emitter length and emitter stripe-number scaling are used to shift simultaneously the optimum noise and optimum source impedance to a point that is close to 50 Ω. Via this method, not only is the optimal transistor size for low-noise applications obtained, but the matching network is simplified to reduce the losses of passive networks and the chip area. Based on experimental results, optimum SiGe HBTs and bias suitable for low-noise amplifiers (LNAs) are determined. Via the comparison of the state-of-the-art SiGe LNAs, it is confirmed that this method is effective to obtain better performances. Using the same method, the optimum device size at any bias and any frequency for low-noise applications can also be achieved.