Current board technologies are inherently performance-limited (FR-4) or cost-prohibitive (Al2O3/AlN). New package or board materials with low CTE and high elastic modulus are needed for the next generation of high-performance convergent Microsystems to be able to fabricate ultra high-density wiring without big capture pads and to assemble area-array flip-chips with minimal stress on solder joint or perhaps completely eliminate underfills around the solder joint. A novel manufacturing process has been demonstrated to yield large-area thin carbon-silicon carbide (C-SiC) based composite boards with potentially low cost and desired thermomechanical properties - ultra high modulus, Si-matched CTE and large-area manufacturability. The reliability performance of this material was evaluated with flip chip test vehicle using conventional epoxies and advanced dielectrics such as BCB and PPE. Bumped dies were assembled and liquid-liquid thermal shock tests and Shadow Moire measurements were carried out to assess the solder joint reliability of these boards. In parallel with experiments, numerical models were also developed to analyze warpage, dielectric cracking and solder fatigue failure, and provide design guidelines. Though boards with Si-matched CTE are essential to lower the solder joint strains, they result in a high CTE mismatch between the build-up dielectrics and board, generating higher stresses in the dielectric which could lead to cracking. In this work, we show that dielectric cracking can be minimized with stiffer boards and thinner build-up layers. Based on the results, it can be inferred that high board stiffness and low CTE (∼3-4 ppm/°C) are needed to ensure reliability of high-density packages without the use of underfill. The test vehicle evaluation supported by modeling results indicate that the novel low-cost large-area processable ceramic matrix composite (C-SiC) has potential to be a promising candidate substrate material for next-generation microsystems.