Chip scale packaging (CSP) is emerging as a major player within the semiconductor packaging market. Processing in the back-end requires optimizing the use of intermediate carrier configurations such as tape-in-carrier and strip-based substrates. This optimization of carrier configurations must occur in all processes related to CSP assembly, including die attach, wire bond, encapsulation, ball attach, laser mark, singulate, inspect, and test. CSP is considered an SMT and, as such, can be processed using existing lines. However, CSP is different from SMT and has its own assembly problems. One of the critical problems is that, with thinner package profile requirement, thinner substrate is necessary. Another important problem that should be considered is the failure of solder joints because of the coefficient of thermal expansion mismatch among the substrate, lead packages, and the board when the thermal load is severe. To address this point, several studies using moire interferometry have been conducted to measure thermal deformations that accumulate during thermal cycles.