For pt. II, see ibid., vol. 47, p. 2068-77 (2000). A new, complete physical model for the transient response of a high-speed global interconnect is rigorously derived. This work improves an earlier model by including a capacitive load termination to a distributed resistance-inductance capacitance (RLC) line, which more accurately models on-chip and off-chip high-speed global wires that drive large capacitive loads. In addition to key physical insight, the new transient expressions presented in this paper provide a quick and accurate estimation of interconnect time delay and crosstalk, which is necessary for rapid design space exploration for global wiring networks in future gigascale integration (GSI) systems.