Some of the more pertinent engineering aspects relating to the design of magnetic film destructive readout (DRO) memories are given, together with a brief reference to nondestructive readout memories. The technical discussion centers primarily on three major areas: 1) storage element characteristics such as skew, dispersion, disturb threshold, and magnetostriction, and how these relate to element fabrication and memory design; 2) memory plane design, with reference to primary effects of eddy currents, fringing fields, and sense line arrangements; 3) special circuit considerations as they relate to film memories. Much of the information presented is general enough to apply to various design approaches. However, specific examples and results obtained with production models of the FFM-202 memory system are used for purposes of illustration. A number of these 300-ns memories are now operating in the field, and current margins obtainable have been superior to those of coincident current core memories. DRO magnetic film memories are presently used in data processing equipment mainly as scratchpads, either as internal stores or as high-speed input/output buffers. However, the real impact of thin film units will be felt when they are commercially available as relatively large building-block modules in the range of 4096 words of 74 bits, at speeds of 200 to 400 ns and at costs competitive with one μs coincident current core memories. The present low costs of semiconductors have alleviated most of the disadvantages of word organization, particularly in magnetic films where only a relatively low-power, unipolar word pulse is needed. Also, the associated low drive power reduces heat dissipation and makes simpler a more compact modular design. This is needed to reduce logic delays in large capacity, high-speed systems. In order to obtain a large capacity, low-cost film memory, primary engineering problems involving the memory stack must be solved. As an example of one desirable approach, a plane design with increased bit density (which results in reduced costs per bit and shorter delays) is described, together with some preliminary results obtained.