For a large-capacity large-size bubble chip, various operating parameter nonuniformities across the chip as well as garnet material and device processing inhomogeneities could be a source of considerable bias margin loss. An example is chip temperature nonuniformity due to detector heating. In an attempt to estimate the chip margin loss due to local temperature nonuniformities, temperature distributions in a Mbit chip have been mapped as a function of detector current amplitude. Temperatures at several regions in the chip were monitored by measuring the resistance of active device components, such as transfer-in gate and replicate/transfer-out gate conductors, and detectors themselves that are of full-shorted 200-element chevron stretchar type. A simple physical model has been developed which, together with various measured local temperatures, provides complete two-dimensional mapping of temperature distributions in the chip. Nonnegligible temperature differences are shown to exist among minor loops (especially at the replicate/transfer-out gate), and those minor loops located close to the detectors are shown to suffer considerable margin losses even at moderate detector-current amplitudes. Operating margin measurements of the minor loops have confirmed the finding.