In this paper, finite state machine (FSM) optimization for a system-on-chip (SoC) interconnection is presented. In the used interconnection architecture, the same interface block is used repeatedly and, therefore, optimization of the interface for synthesis is a very critical implementation issue. However, low-level hand-optimization is not desirable and, therefore, optimization should be performed in the high-level description or automatically in the synthesis process. The results of this paper suggest that design space exploration leads to substantial improvements when constructing complex SoCs. Ideas on how to support this automatically with FSM optimization are shown.