Technology awareness and modeling is important in all areas of mixed-signal and RF design. This forum intends to provide a holistic overview and discussion spanning a variety of important topics in device modeling, reliability and simulation in next-generation CMOS. It begins with an analog/RF-centric comparison between FinFET and ultra-thin-body SOI technology. The next two talks then venture into bias stress and Electrostatic Discharge Protection (ESD), which are two issues of ever-increasing importance for future scaling. The fourth presentation discusses the latest developments surrounding the popular BSIM transistor model, and explains how this new model can be efficiently coupled to the analog/RF design process. Motivated by their increasing significance in integrated RF transceivers, the next talk outlines a future roadmap for passive components in scaled technologies. Then, we expand upon modeling challenges that arise when components are stacked in three dimensions. Finally, this series of modeling talks is rounded up by two comprehensive presentations that summarize key challenges from the foundry and EDA tool vendor perspectives.