This 512 Mb DDR2 SDRAM is designed with the DDR2 features being standardized by JEDEC. The SDRAM uses a four-quadrant architecture, each 128 Mb quadrant containing 16 k rows x 8 k columns. A 6.6F/sup 2/ (2.2F×3F) deep trench cell with a vertical access gate is employed. The wordline pitch is increased by 10% and the bitline pitch by 50%, yet the cell area is reduced to as little as 82.5% that of the 8F/sup 2/ cell. Each 128 Mb quadrant is partitioned into sixteen 8 Mb blocks horizontally. It is also partitioned into sixteen 8 Mb segments vertically. These partitions configure a 512 kb array, each containing 1024 wordlines (WLs) and 512 bitlines (BLs). A total of 16×16 512 kb arrays are arranged in a matrix in each 128 Mb quadrant. A hierarchical row decoder block (HRDEC) drives a master wordline (MWL) on a 2nd level metal (M2). A local wordline decoder block (LRDEC) then redrives the MWL to control a local W-silicide wordline (LWL).