A technique to extract the off-state floating-body (FB) voltage of silicon-on-insulator (SOI) CMOS devices is presented. The bias dependent S-parameter measurements of a single standard FB SOI device and its equivalent circuit, along with the capacitance-voltage (C-V) measurements between the drain and source of the same device, are used to determine the FB voltage. No special test structure design is needed. The technique proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depicted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage.