By Topic

Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Cheoljon Jang ; Dept. of Electron. Comput. Eng., Hanyang Univ., Seoul, South Korea ; Jaehwan Kim ; Byunggyu Ahn ; Jongwha Chong

Author(s)

Cheoljon Jang
Dept. of Electron. Comput. Eng., Hanyang Univ., Seoul, South Korea
Jaehwan Kim ; Byunggyu Ahn ; Jongwha Chong