Timing compensation between the clock period and datapath delay in the presence of resonant supply noise has drawn a great deal of attention from the circuit design community. This effect, which is often referred to as the clock data compensation effect, manifests itself as an increase in maximum operating frequency for high performance microprocessors. In this work, we propose an adaptive phase-shifting PLL that can achieve optimal clock data compensation by digitally programming the supply noise sensitivity and the phase shift of the PLL clock period. Measurement results from a 1.2 V, 65 nm test chip demonstrate a 3.4-7.3% improvement in the maximum operating frequency across different clock distribution designs and resonant frequencies. A mathematical framework for simulating the performance of the adaptive phase-shifting PLL is presented for better insight on how the proposed PLL performs when used in different clock network configurations. In addition, the impact of the proposed technique on PLL stability as well as its effectiveness in a 32 nm process has been explored.