A frequency tripler designed for V-band signal generation and millimeter-wave applications has been implemented by using CMOS 90 nm technology. In order to improve the output power level with high conversion efficiency, we use a cascode circuit topology to design a frequency tripler. Based on the small-signal analysis and the large-signal harmonic simulation, the optimized characteristics such as conversion loss, output bandwidth, and the output power response can be achieved under the proper biases in this circuit. The tripler exhibits a conversion loss of 9 dB at 54 GHz for an input power of 4 dBm. The dc power consumption of the circuit is about 5.4 mW with a 1.8 V dc supply. The measured output 3-dB bandwidth is approximated to 10.5 GHz, ranging from 49.5 GHz to 60 GHz. The fundamental- and second-order suppressions both are better than 31 dBc. A high saturation output power can be achieved to -1.4 dBm when injecting a signal power of 10 dBm.