A low-power receiver circuit in 32 nm SOI CMOS is presented, which is intended to be used in a source-synchronous link configuration. The design of the receiver was optimized for power owing to the assumption that a link protocol enables a periodic calibration during which the circuit does not have to deliver valid data. In addition, it is shown that the transceiver power and the effect of high-frequency transmit jitter can be reduced by implementing a linear equalizer only on the receive side and avoiding a transmit feed-forward equalizer (TX-FFE). On the circuit level, the receiver uses a switched-capacitor (SC) approach for the implementation of an 8-tap decision-feedback equalizer (DFE). The SC-DFE improves the timing margin relative to previous DFE implementations with current feedback, and leads to a digital-style circuit implementation with compact layout. The receiver was measured at data rates up to 13.5 Gb/s, where error free operation was verified with a PRBS-31 sequence and a channel with 32 dB attenuation at Nyquist. With the clock generation circuits amortized over eight lanes, the receiver circuit consumes 2.6 mW/Gbps from a 1.1 V supply while running at 12.5 Gb/s.