A low complexity baseband transceiver design for power line communication is presented. The proposed baseband transceiver adopts an M-ary Bi-Orthogonal Keying (MBOK) based Direct-Sequence Spread Spectrum (DSSS) modulation scheme. The front end signal is further modulated by a FSK scheme to combat serious channel impairments in power line network. No A/D or D/A converters are required and a simple dual-phase sampling technique is employed for timing recovery. Occupying a bandwidth of 400 kHz, the design has a 200 kHz chip rate and is capable of supporting a reliable 100 kbps data rate. The BER can be lower than 10-3 when the SNR value reaches 20dB. The FPGA implementation results indicate the baseband kernel design consumes less than 3,000 logic gates and features a low circuit complexity and protocol robust solution.