Dynamic power is a keenly analysed design parameter in SRAM memory design especially in low power battery operated systems. A simple way to reduce dynamic power (and leakage power) is to lower the operating voltage to the minimum possible for a given operating speed requirement. The transistor threshold voltages ultimately define the lowest operating voltage possible but memory circuits have a number of specific issues which usually limit minimum operating voltages to higher then the theoretical minimum. One such issue is the write operation to a standard 6T SRAM bit cell. This paper explains the techniques and write assist circuits used in the level 1 cache sub-system in a GHz+ Dual Core ARM Cortex A9 CPU on a 32nm LP process to support low voltage operation. Two independently enabled techniques are implemented; a supply boosting scheme to drive the memory above the nominal supply voltage and a novel voltage lowering scheme to reduce the voltage supply to the bit cells. Both are discussed and the improvement in minimum functional operating voltage is reported.