The design of the first-level trigger processor for the ZEUS calorimeter is discussed. This processor accepts data from the 13000 photomultipliers of the calorimeter, which is topologically divided into 16 regions, and after regional preprocessing performs logical and numerical operations that cross regional boundaries. Because the crossing period at a HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100 K emitter-coupled logic (ECL), advanced CMOS discrete devices and programmable gate arrays, and it operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flow into the processor at a rate of 5.2 GB/s, and processed data flow from the processor to the global first-level trigger at a rate of 700 MB/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor.