Scaling supply voltage is an efficient technique to achieve low energy delay product (EDP). This paper investigates static CMOS, DCVSL, CPL and TG logic full adders in sub-threshold and super-threshold region in terms of low EDP. All circuits are simulated with HSPICE at a PTM 65nm CMOS technology by varying supply voltages from 0.2V to 1.1V with 0.1V steps. The simulation results demonstrate that lowering supply voltage is advantageous, especially in medium-voltage region (700mv-800mv) which yields the best EDP. In addition, it is shown that the optimum supply voltage of the full adders varies slightly with logic style.