In this paper, we propose a memory and performance optimized architecture to accelerate the operation speed of adaptive deblocking filter (DF) for H.264/JVT/AVC video coding. With the proposed processing order, we can reduce not only the number of internal buffer but also the size of the internal SRAM. Two 4Ã4 internal buffer with MUXs and a 32Ã16 internal SRAM are needed for the buffering operation of DF with I/O bandwidth of 32 bit. The filtering cycles of the proposed DF are 192 clocks in loading/storing and filtering operations. Proposed architecture can be processed in real-time for 1080HD (1920Ã1088@30 fps) at a 70 MHz clock frequency.