This paper describes the circuit schemes used to substitute redundant storage locations for defective ones found during testing. Word or bit lines are added along with appropriate bit steering circuitry to allow the replacement of a defective word or bit line. On-chip storage elements are “set” by the tester and used to store the binary addresses of the failing word or bit lines, which are then compared to the incoming addresses by the redundancy circuitry. This circuitry then activates the replacement word or bit lines and, by various means described, steers out the defective ones. A variation is described briefly which includes a word redundant circuit scheme that provides no penalty in memory access time by using separate sense amplifiers for the redundant lines.
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