This paper describes a sense scheme for use on high-density one-device cell field effect transistor random access memories (FET RAMs). The high-sensitivity threshold-independent cross-coupled charge-transfer sense amplifier and latch is used. The IBM 64K-bit one-device dynamic memory cell FET RAM chip design is used as the vehicle for the discussion. Adaptations made on the sense amplifier and latch for use with the sense scheme are discussed. Also described are 1) dummy cell design, 2) subthreshold leakage considerations, 3) single-ended input/output (I/O) circuitry sensing and ramifications, 4) multiple cycle signal degradations, and 5) a maximum supply voltage (VH) buffer circuit sense scheme improvement.
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