The minimization of system clock skew is critical to the overall performance of high-speed computer systems. This paper discusses the statistical clock skew calculation methodology employed in the analysis of the IBM Enterprise System/9000™ (ES/9000™) computer systems. Comparisons made to a worst-case design approach show the advantages of a statistical clock skew calculation and its use in the timing analysis of ES/9000 systems. Design techniques that aid in the minimization of system clock skew are discussed throughout this paper. While many details concerning these design techniques and the statistical clock skew calculation methodology are tutorial in nature and have been used in the design of past IBM high-end machines, it is hoped that this paper will give the reader a useful understanding of the major considerations affecting the clock system and its application to an ES/9000 system.
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