The critical charge, Qcrit, of a memory array storage cell is defined as the largest charge that can be injected without changing the cell's logic state. The Qcrit of a Schottky-coupled complementary bipolar SRAM array is evaluated in detail. An operational definition of critical charge is made, and the critical charge for the cell is determined by circuit simulation. The dependence of critical charge on upset-pulse wave shape, statistical variations of power supply voltage, temperature gradients, manufacturing process tolerances, and design-related influences due to word- and drain-line resistance was also calculated. A 2× range in Qcrit is obtained for the SRAM memory array cell from simulations of normal (±3σ) variations in manufacturing process tolerances, the shape of the upset current pulse, and local cell temperatures. Using SEMM, a 60× variation of the soft-error rate (SER) is obtained for this range in Qcrit. The calculated SER is compared to experimental values for the chip obtained by accelerated testing. It is concluded that a range in values of the critical charge of a cell due to normal manufacturing and operating tolerances must be considered when calculating soft-error rates for a chip.
Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.