Progress in MOS integrated-circuit technology has been largely dominated by the scaling of device feature sizes. For the production of advanced CMOS logic devices with minimum feature sizes in the sub-0.1-µm regime, one of the areas of device fabrication that will limit future CMOS scaling is the continued reduction in the gate dielectric film thickness. This issue of the IBM Journal of Research and Development focuses on the processes and materials that are required to produce reliable CMOS devices with ultrathin gate dielectric films.
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