Theoretical analysis and bandwidth enhancement of the cascaded double-stage distributed amplifiers (CDSDA) are presented. The characteristics of the general cascaded multi-stage distributed amplifiers (CMSDA) with open idle drain terminations at intersections for a high gain are investigated with lossy artificial lumped line models. This reveals the inherent bandwidth limitation of the CMSDA due to interference from the reverse wave reflection at the open drain terminations. To achieve simultaneous high gain and bandwidth, drain line impedance tapering is introduced to enable a counterbalance of the reverse wave by partial reflection of the forward wave at each of the impedance junctions. Detailed analysis and design considerations are provided where it is shown that typical parasitic drain capacitance of transistors makes the drain line tapering practically viable for the CMSDA up to the double-stage configuration. Extensive validation of the theoretical analysis and the tapered drain line technique are given through the experiment of a 3.2 GHz 25.2-dB hybrid CDSDA, and through the simulation of a 13.8 GHz 14-dB CDSDA using a 0.18 ??m CMOS process.