As critical dimensions (CD) for semiconductor devices shrink to a few tens of nanometers, the line edge roughness (LER) and linewidth roughness (LWR) becomes a critical issue. For this study, we used a new 3D CD-AFM which enables us to characterize LER and LWR along the features after each technological step of standard gate patterning processes. Isolated lines with CDs going from 20nm and 100nm were written with an e-beam lithography tool. First, we transfer the resist mask into silicon to determine the influence of different plasma chemistries on LER. Then, the resist mask is transferred into a standard CMOS gate stack: SiO2 hard mask, polysilicon, dielectric gate. The results after e-beam lithography show that the LWR measured at the bottom of the pattern is higher than the one measured at the middle. It can be attributed to the effect of backscattered electrons. Then, we show that for smaller dimensions, the trimming that occurs during the hard mask opening process weakens the resist and increases drastically the LWR in the polysilicon. This puts forward one limitation of standard processes for aggressive gate patterning. Finally, we do not observe any obvious trend on LER and LWR after the characterization of features coming from two different silicon etching chemistries. This conclusion is surprising. We attributed it to the tip size limitation in sidewall roughness detection on silicon.