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Trench etching and filling technique for the isolation between the control (low voltage) and the power (high voltage) region in power integrated circuits was investigated. This technique consists of a deep trench formation (8.0 μm) with positive etching using 45% He–O2 of the HBr and SiF4 chemistries followed by filling and global planarization with the chemical mechanical polishing technique. The novel trench etching technique provides better surface quality of 3.1 Å roughness measured with atomic force microscopy. The filling and global planarization results in lower leakage current less than 1 nA at the supplying voltage of 400 V. © 2000 American Vacuum Society.
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