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We report the fabrication of dual insulated gate thin-film transistors with chemical-bath deposited cadmium sulfide active layers. The cadmium sulfide was deposited from solution onto thermally oxidized silicon wafers to form the first semiconductor–dielectric interface. The terpolymer poly(tetrafluoroethylene-co-vinylidenefluoride-co-propylene) was laminated onto the semiconductor to create the second semiconductor–dielectric interface. This device geometry allows direct comparison of the behavior of the accumulated charge at these two very different interfaces. The mobility values for these devices are in the 0.1–1 cm2/Vs range, while the on/off ratios vary from 102 to 105. The ability to laminate a dielectric to a semiconductor enables new processing routes for large area transistor arrays. © 2004 American Institute of Physics.
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