Two of the most significant factors in the success of todaypsilas system-on-chip (SoC) designs are the ability to deliver efficient access to off-chip high speed memory and the ability to be compatible with several different interface-timings of several different sorts of memories. This paper introduces a novel general external memory interface (GEMI) architecture for the high performance and high flexibility memory interface. Several techniques and methods, i.e. data and command buffers based on asynchronous FIFO, optimized bank management, multiple bus width adaptation, improved WISHBONE bus interface, optimized array-structure data accessing, are proposed in this paper for fulfilling the requirements mentioned above. And the performance improvement by using of our architecture and techniques is analyzed. At the end of the paper, the simulation and tape-out results are provided. The whole implementation of architecture is proven to be not only functional and efficient, but also flexible, programmable and reusable by simulation and silicon verification.