This successive approximation register ADC uses time-interleaving to gain the energy advantage of slower circuits (reduced supply voltage and improved bias points) without sacrificing high speed operation. The drawbacks of interleaving are addressed through architectural solutions. Channel redundancy counteracts the severe yield loss that parallel circuits experience due to local variation. Clock partitioning restricts the distribution of the precise, high-speed sampling clock to three centrally located sampling networks. Only a low frequency clock is distributed across the majority of die area. The skew-resistant global top-plate sampling network is extended to allow overlapped sampling windows without introducing extra sources of crosstalk. The 36 -way interleaved 5-bit ADC operates with a core voltage of 800 mV and consumes 1.20 mW total power at 250 MS/s. At Nyquist, the SNDR is 28.4 dB. The 6 redundant channels (17% overhead) increase the yield of the 24 measured chips from 42% to 88%.