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Gate oxide protection in HV CMOS/DMOS integrated circuits: Design and experimental results

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3 Author(s)
R. Chebli ; Department of Electrical Engineering, École Polytechnique de Montréal, POB 6079, Station Centre-Ville Montreal, Quebec, CANADA H3C 3A7 ; M. Sawan ; Y. Savaria

Author(s)

R. Chebli
Department of Electrical Engineering, École Polytechnique de Montréal, POB 6079, Station Centre-Ville Montreal, Quebec, CANADA H3C 3A7
M. Sawan ; Y. Savaria