This paper proposes an approach for reducing additional signals in signal transition graph (STG) based logic synthesis for asynchronous control circuits. The proposed scheme introduces a template based method in state encoding process to insert additional signals to STG with a small number. According to our method, complete state coding (CSC) property can be satisfied without using state graph tracing which is used in classical state based method. Our method is useful for large scale asynchronous controllers, and also it can guarantee the other relevant properties, such as persistency and consistency. Our process begins with an encoding STG using Petri-net level in order to form a template STG. Then the projection to each non-input signals from an original STG is done. After that, we trace the projection to smaller state space. If the small state space shows conflicts, we have to insert balance signals from template STG. Unbalance signals are inserted after in case the space still shows conflicts. Finally, we can get the STG with appropriate insertion points which is used to be projected for CSC support on each non-input signals. Asynchronous DMA controller is an example of our proposed method. The final part of this paper is concluded with a complexity comparison between our template based method with state based method and structural encoding method. It shows that the number of iterative signal removal according to our method is less than others.
Digital System Engineering Laboratory (DSEL), Department of Computer Engineering, Faculty of Engineering, Chulalongkorn University, 254 Phyathai Road, Pathumwan, Bangkok, 10330 Thailand