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Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution

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2 Author(s)
Ming-Dou Ker ; Nanoelectronics & Gigascale Systems Laboratory, Institute of Electronics, Nation Chiao-Tung University, 1001 Ta-Hsueh Road, Hsinchu, Taiwan ; Cheng-Cheng Yen

Author(s)

Ming-Dou Ker
Nanoelectronics & Gigascale Systems Laboratory, Institute of Electronics, Nation Chiao-Tung University, 1001 Ta-Hsueh Road, Hsinchu, Taiwan
Cheng-Cheng Yen