A detailed study was conducted of the tradeoffs involved in the design of silicon planar transistors tolerant to fast-neutron irradiation up to 1 ?? 1015 nvt. Initial measurements made on irradiated 2N918 transistors indicated that breakdown voltage and collector current range must be sacrificed in order to improve device radiation resistance. The tradeoffs relating post-irradiation hFE to transistor fT, saturation region characteristics to breakdown voltage, and usable collector current range to length of emitter periphery are discussed in detail. The cptirn design is a high frequency, lcw breakdawn voltage transistor with a narrow usable current range. Transistors were fabricated having hFE greater than 5 over a wide tenwrature range after irradiation to 1 ?? 1015 nvt.