This paper discusses design methodology for a module-wise dynamic voltage and frequency scaling (DVFS) technique which adjusts the supply voltage for a module appropriately to reduce the power dissipation. A circuit is able to work even when the supply voltage is in transition, by using our dynamic de-skewing system (DDS). We propose a clock design methodology to minimize the intermodule clock skew for solving one of the major design issues in the module-wise DVFS. We also describe a method of determining the minimum supply voltage value for a module. We lead the issue to a problem of solving simultaneous polynomial inequalities. Our experimental results show that the module-wise DVFS can reduce 53% power compared with the chip-wise DVFS, and 17% more reduction was achieved by applying the minimum supply voltage proposed.