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Low-power way-predicting cache using valid-bit pre-decision for parallel architectures

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2 Author(s)
Hsin-Chuan Chen ; Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan ; Jen-Shiun Chiang

Author(s)

Hsin-Chuan Chen
Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan
Jen-Shiun Chiang