Multi-Gb/s high-speed links face significant challenges in keeping up with the increase in desired data rates. In the evaluation of achievable data rates, it is necessary to include both link-specific noise sources and implementation driven constraints. We construct models of these noise sources and constraints in order to estimate the theoretical limits of typical high-speed link channels. In order to estimate the data rates of practical baseband architectures, we solve the power constrained optimal linear precoding problem and formulate a bit-error rate (BER) driven optimization, including all link-specific noise sources. The problem is shown to be quasiconcave, hence, a globally optimal solution is guaranteed. Using this optimization framework, we show that practical data rates are mainly limited by inter-symbol interference (ISI) due to complexity constraints on the number of precoder and equalizer taps. After these constraints are removed, we further show that slicer resolution and sampling jitter are limiting the higher bandwidth utilization provided by multi-level modulations. Better circuits are needed to improve the bandwidth utilization to more than 2bits/dimension in baseband.