The range of distributed real-time and embedded (DRE) system applications has continued to expand at a vigorous rate. Designers of DRE systems are constantly challenged to provide new capabilities to meet expanding requirements and increased computational needs, while under pressure to provide constantly improving price/performance ratios and shorter times to market. Recently emerging hybrid chips containing both CPUs and FPGA components have the potential to enjoy significant economies of scale, while enabling system designers to include a significant amount of specialization within the FPGA component. However, realizing the promise of these new hybrid CPU/FPGA chips will require programming models supporting a far more integrated view of CPU and FPGA based application components than that provided by current methods. This paper describes methods we are developing for supporting a multithreaded programming model providing strongly integrated interface to CPU and FPGA based component threads.