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A novel technique for full-wave modeling of large-scale three-dimensional high-speed on/off-chip interconnect structures

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7 Author(s)
Jiao, D. ; Logic Technol. Dev., Intel Corp., Santa Clara, CA, USA ; Mazumder, M. ; Chakravarty, S. ; Dai, C.
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Author(s)

Jiao, D.
Logic Technol. Dev., Intel Corp., Santa Clara, CA, USA
Mazumder, M. ; Chakravarty, S. ; Dai, C. ; Kobrinsky, Mauro J. ; Harmes, M.C. ; List, S.